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general description the max3892 serializer is ideal for converting 4-bit- wide, 622mbps parallel data to 2.5gbps serial data in dwdm and sonet/sdh applications. a 4 ? 4-bit fifo allows for any static delay between the parallel output clock and parallel input clock. delay variation up to a unit interval (ui) is allowed after reset. a fully integrated phase-locked loop (pll) synthesizes an internal 2.5ghz serial clock from a 622mhz, 155.5mhz, 77.8mhz, or 38.9mhz reference clock. a selectable dual vco allows excellent jitter performance at both sonet and forward-error correction (fec) data rates. operating from a single 3.3v supply, this device accepts low-voltage differential-signal (lvds) clock and data inputs for interfacing with high-speed digital circuit- ry, and delivers current-mode logic (cml) serial data and clock outputs. a loopback data output is provided to facilitate system diagnostic testing. the max3892 is available in the extended temperature range (-40? to +85?) in 44-pin qfn and tqfn packages. applications sonet/sdh oc-48 transmission systems wdm transponders add/drop multiplexers dense digital cross-connects backplane interconnects features ? single +3.3v supply ? 455mw power consumption ? 1.4ps rms maximum jitter generation ? 4 ? 4-bit fifo input buffer ? 622mbps/666mbps parallel to 2.5gbps/2.7gbps serial conversion ? 622mhz/667mhz or 311mhz/333mhz clock input ? on-chip clock synthesizer ? multiple clock reference frequencies: (622.08mhz, 155.52mhz, 77.76mhz, 38.88mhz) or (666.51mhz, 166.63mhz, 83.31mhz, 41.66mhz) ? lvds parallel clock and data inputs ? cml serial data and clock outputs ? additional cml output for system loopback testing max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis ________________________________________________________________ maxim integrated products 1 ordering information 19-2215; rev 6; 10/07 evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin- package pkg code max3892egh -40 c to +85 c 44 qfn g4477-3 max3892eth+ -40 c to +85 c 44 tqfn t4477-3 pdi0+ pdi0- pdi3+ pdi3- rclk+ rclk- clkset fil reset rateset sdo+ sdo- sclko+ sclko- slben slbo+ slbo- pclki+ pclki- pclko+ pclko- mode fifoerror lol sonet/sdh framer lvpecl lvds lvds lvds cml cml cml vccvco vccvco laser driver optional for system loopback test ttl c z this symbol represents a transmission line of characteristic impedance z o = 50 . slbpd max3273 max3882 v cc max3892 1:4 deserializer with cdr 100 typical application circuit + denotes a lead-free package.
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc = +3.0v to +3.6v, t a = -40? to +85?. typical values are at v cc = +3.3v, differential lvds load = 100 ?%, t a = +25?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. supply voltage v cc , vcco, vccvco .....................-0.5v to +5v all inputs and fil .......................................-0.5v to (v cc + 0.5v) lvds output voltage (pclko?................-0.5v to (v cc + 0.5v) cml output current (sdo? sclko? slbo? ................22ma continuous power dissipation (t a = +85?) 44-pin qfn (derate 25mw/? above +85?) ............1625mw operating temperature range ...........................-40? to +85? storage temperature range .............................-55? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units supply current i cc (note 2) 138 190 ma lvds input specifications (pdi[3..0] , pclki ) input voltage range v i 0 2400 mv differential input voltage |v id | 100 mv input common-mode current lvds input v os = 1.2v 61 ? threshold hysteresis 45 mv differential input resistance r in 83 100 117 lvpecl input specifications (rclk ) input high voltage v ih v cc - 1.16 v cc - 0.88 v input low voltage v il v cc - 1.81 v cc - 1.48 v input bias voltage v cc - 1.3 v single-ended input resistance >1.0 k differential input voltage swing 300 1900 mv p-p lvds output specifications (pclko ) output high voltage v oh 1.475 v output low voltage v ol 0.925 v differential output voltage |v od | 250 400 mv change in magnitude of differential output voltage for complementary states |v od | 25 mv offset output voltage 1.125 1.275 v change in magnitude of output offset voltage for complementary states |v os | 25 mv
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis _______________________________________________________________________________________ 3 ac electrical characteristics (v cc = +3.0v to +3.6v, t a = -40? to +85?. typical values are at v cc = +3.3v, differential lvds loads = 100 ?%, cml loads = 50 ?%, t a = +25?, unless otherwise noted.) (note 3) dc electrical characteristics (continued) (v cc = +3.0v to +3.6v, t a = -40? to +85?. typical values are at v cc = +3.3v, differential lvds load = 100 ?%, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units differential output resistance 80 140 output current shorted together 12 ma output current shorted to ground 40 ma cml output specifications (sdo , sclko , slbo? differential output r l = 100 differential 640 800 1000 mv p-p differential output resistance 83 100 117 output common-mode voltage r l = 50 to v cc v cc - 0.2 v lvttl specifications (reset, rateset, slben, slbpd fifoerror, lol ) input high voltage v ih 2.0 v input low voltage v il 0.8 v input high current i ih -30 +10 ? input low current i il -50 +10 ? output high voltage v oh i oh = 20? 2.4 v cc v output low voltage v ol i ol = 1ma 0.4 v programming inputs (clkset, mode) input current input = 0 or v cc -500 +500 ? parameter symbol conditions min typ max units parallel input specifications (pdi , pclki ) rateset = gnd 622 parallel input data rate rateset = v cc 666 mbps mode = open or v cc 622 parallel input clock rate mode = short or 30k to gnd 311 mhz parallel input setup time t su (note 4) -94 ps parallel input hold time t h (note 4) 300 ps parallel clock output specifications (pclko ) parallel clock output rise/fall time t r , t f 20% to 80% 100 200 ps parallel clock output duty cycle 46 54 % serial output specifications (sdo , sclko ) rateset = gnd 2.488 serial output data rate rateset = v cc 2.666 gbps serial data output rise/fall time t r , t f 20% to 80% 80 ps serial output clock to data delay t clk-q (note 5) -25 25 ps
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis 4 _______________________________________________________________________________________ note 1: specifications at -40? are guaranteed by design and characterization. note 2: measured with slbo/clk622 and sclk outputs disabled and cml outputs open. note 3: ac characteristics are guaranteed by design and characterization. note 4: in 622mhz clock mode, the parallel data is clocked in by the rising edge of the 622mhz/666mhz parallel clock input. in the 311mhz clock mode, the parallel data is clocked in on both the rising and falling edges of the clock. the parallel input setup and hold time increases by 60ps if the duty cycle is between 48% to 52% in 311mhz mode (figure 1). note 5: relative to the falling edge of the sclko. note 6: measurement bandwidth is bw = 12khz to 20mhz. note 7: measured with 00001111 pattern, rclk to pclki/pdi[3:0] phase approximately 40ps. see the jitter generation vs. rclk to pclk/pdi[3:0] phase plot in the typical operating characteristics section. note 8: deterministic jitter includes pattern-dependent jitter and pulse-width distortion. measured using a 2 7 - 1 prbs pattern with 96 consecutive identical digits. ac electrical characteristics (continued) (v cc = +3.0v to +3.6v, t a = -40? to +85?. typical values are at v cc = +3.3v, differential lvds loads = 100 ?%, cml loads = 50 ?%, t a = +25?, unless otherwise noted.) (note 3) parameter symbol conditions min typ max units serial clock output jitter generation jg (notes 6 and 7) 1.0 1.4 ps rms serial data output random jitter rj (note 7) 1.4 ps rms serial data output deterministic jitter dj (note 8) 19 ps p-p reference clock input specifications (rclk) reference clock frequency tolerance 100 ppm reference clock input duty cycle 30 70 % reset inputs (reset) minimum pulse width of fifo reset ui is pclko period 4 ui tolerated drift between pclki and pclko after reset ui is pclko period 1ui
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis _______________________________________________________________________________________ 5 120 135 130 125 145 140 165 160 155 150 170 -40 -20 0 20 40 60 80 100 supply current vs. temperature max3892 toc01 temperature ( c) supply current (ma) 50ps/div electrical eye diagram max3892 toc02 pattern 2 13 -1 prbs data rate = 2.5gbps 40 0 10 1k 10k power-supply jitter generation vs. ripple frequency 10 5 15 20 25 30 35 max3892 toc03 ripple frequency (khz) jitter generation (ps p-p ) 100 100mv p-p 50mv p-p 0 1.5 1.0 0.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 100 50 150 200 250 jitter generation vs. power supply noise amplitude (bw = 2mhz) max3892 toc04 noise amplitude (v p-p ) jitter generation (ps rms ) jitter generation vs. rclk to pclki/pdi[3:0] phase max3892 toc05 rclk to pclki/pdi[3:0] phase (ps) jitter generation (ps rms ) 350 300 250 200 150 100 50 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 0 400 pattern = 00001111 5ps/div serial-data output jitter max3892 toc06 total wideband rms jitter = 1.3ps peak-to-peak jitter = 15.8ps f rclk = 622mhz typical operating characteristics (v cc = +3.3v, cml loads ac-coupled to 50 ?%, t a = +25?, unless otherwise noted.) pin description pin name function 1, 16, 22, 27, 33, 44 gnd supply ground 2, 5, 8, 11 vcco supply voltage for outputs +3.3v. add bypass capacitors near these pins before connecting to the v cc power plane. 3 sclko- negative serial clock output, cml 2.488ghz or 2.666ghz 4 sclko+ positive serial clock output, cml 2.488ghz or 2.666ghz 6 sdo- negative serial data output, cml 2.488gbps or 2.666gbps 7 sdo+ positive serial data output, cml 2.488gbps or 2.666gbps
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis 6 _______________________________________________________________________________________ pin description (continued) pin name function 9 slbo- negative system loop-back output or 622mhz/666mhz clock output. select cml data or clock as shown in table 1. 10 slbo+ positive system loop-back output or 622mhz/666mhz clock output. select cml data or clock as shown in table 1. 12 slbpd system loopback power down, ttl input. slpd = high activates the system loopback output driver; slbpd = low powers down the loop-back output driver. 13 slben system loop-back enable input, ttl input. slben = high activates the system loop-back output; slben = low activates the 622mhz/666mhz reference clock output. 14 reset fifo reset, ttl input. an active-high reset recenters the fifo to tolerate maximum skew between pclki and pclko. 15 fifoerror fifo error indicator, ttl output. active high when the read/write clocks access the same fifo address. this signal may be used to control reset. 17, 28, 36, 43 v cc supply voltage, +3.3v 18 lol loss of lock, ttl output. an active low indicates that the vco and reference frequency differ by 500ppm. 19 mode clock control input: mode = gnd; f pclki = 311.04mhz/333mhz with sclko active mode = 30k to gnd; f pclki = 311.04mhz/333mhz with sclko off mode = open (float); f pclki = 622.08mhz/666mhz with sclko off mode = v cc ; f pclki = 622.08mhz/666mhz with sclko active 20 pclki+ positive parallel clock, lvds input. data is written to the input register on the clock rising edge in 622mbps mode and on both rising and falling edges in 311mbps mode (figure 1). 21 pclki- negative parallel clock, lvds input (figure 1). 23, 25, 29, 31 pdi3+ to pdi0+ positive data inputs, lvds (622mbps or 666mbps) 24, 26, 30, 32 pdi3- to pdi0- negative data inputs, lvds (622mbps or 666mbps) 34 pclko+ positive parallel clock output, lvds. this clock may be 622.08mhz or 666mhz. 35 pclko- negative parallel clock output, lvds. this clock may be 622.08mhz or 666mhz. 37 rclk+ positive reference clock input, lvpecl 38 rclk- negative reference clock input, lvpecl 39 clkset reference clock rate programming pin: clkset = v cc ; rclk = 622.08mhz/666mhz clkset = open (float); rclk = 155.52mhz/167mhz clkset = 30k to gnd; rclk = 77.76mhz/83.3mhz clkset = gnd; rclk = 38.88mhz/41.6mhz 40 rateset data rate select, ttl input. rateset = high for 2.666gbps, rateset = low for 2.488gbps. 41 vccvco supply voltage for vco +3.3v. add bypass capacitors near this pin before connecting to the v cc power plane. 42 fil pll capacitor pin. connect a 0.1? capacitor from this pin to vccvco. ep exposed paddle the exposed paddle must be soldered to ground for proper thermal and electrical operation.
detailed description the max3892 converts 4-bit-wide, 622mbps/667mbps data to 2.5gbps/2.7gbps serial data (figure 2). data is loaded into the 4:1 mux through a 4 ? 4-bit fifo buffer for wide tolerance to clock skew. clock and data inputs are lvds levels while high-speed serial outputs are cml. an internal pll frequency synthesizer generates a serial clock from a low-speed reference clock. low-voltage differential-signal inputs and outputs the max3892 has lvds inputs and outputs for inter- facing with high-speed digital circuitry. the lvds stan- dard is based on the ieee 1596.3 lvds specification. this technology uses differential low-voltage swings to achieve fast transition times, minimized power dissipa- tion, and noise immunity. for proper operation, the par- allel clock lvds outputs (pclko+, pclko-) require 100 differential dc termination between the positive and negative outputs. do not terminate these outputs to ground. the parallel data and parallel clock lvds inputs (pdi+, pdi-, pclki+, pclki-) are internally ter- minated with 100 differential input resistance, and therefore do not require external termination. pecl inputs the reference clock (rclk+, rclk-) has pecl inputs for interfacing to a crystal oscillator with ac or dc con- nections. the rclk inputs are self-biasing to v cc - 1.3v for ac-coupled inputs. only a 100 differential termination resistance must be added when inputs are ac-coupled. current-mode logic outputs the 2.5gbps/2.7gbps data, clock, and system loop- back outputs (sdo+, sdo-, sclko+, sclko-, slbo+, slbo-) of the max3892 are designed using current-mode logic (cml). the configuration of the max3892 cml output circuit includes internal 50 back termination to v cc (figure 3). these outputs are intended to drive a 50 transmission line terminated with a matched load impedance. fifo buffer data is latched into the max3892 by the parallel input clock pclki. the parallel input clock serves as the fifo write clock. the parallel output clock pclko acts as the fifo read clock that loads the 4:1 mux. the fifo allows the read and write clocks to vary by up to ?ui. conditions that result in the read and write clock accessing the same fifo address are indicated by max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis _______________________________________________________________________________________ 7 t su t h t su t h pdi_ 622mhz clock 311mhz clock 1.608ns d3 d2 d1 d0 note: signals shown are differential. for example, pclk0 = (pclk0+) - (pclko-). *pdi3 = d3; pdi2 = d2...pdi0 = d0. pdi3 is the msb and is transmitted first. this figure is not intended to show a specific timing relationship between parallel input data and serial output data. pclki+ - pclki- data in sdo sclko t clk-q data out 2.5ghz clock figure 1. timing diagram
max3892 latching high fifoerror. to clear this condition, reset must be asserted high for at least 4ui. fifoer- ror may be tied directly to the reset input to recen- ter the fifo. after reset, the full elastic range of the fifo is available again. frequency synthesizer the pll synthesizes a 2.5gbps/2.7gbps clock (sclko) from an external reference clock. the pll reference clock (rclk) may be 622.08mhz/666.53mhz, 155.52mhz/166.6mhz, 77.76mhz/83.3mhz or 38.88mhz/41.65mhz as determined by clkset and rateset. see table 2 for the reference fre- quency selection. the parallel output clock pclko is also derived from the synthesizer to be sclko divided by 4. a ttl-compatible loss-of-lock indicator, lol , goes low when the vco is unable to lock to the reference frequency. frequency difference on rclk with respect to the divided down sclko greater than 500ppm is indicated by a low state on lol . when the frequency difference between the clocks is less than 250ppm, lol high indicates a lock condition. system loopback the max3892 is designed to allow system loop-back testing. the loop-back outputs (slbo+, slbo-) of the max3892 may be directly connected to the loop-back inputs of a deserializer (such as the max3882) for sys- tem diagnostics. alternatively, the slbo pins can be programmed to provide a 622mhz reference clock. this reference clock can provide a clock hold-over sig- nal to a clock and data recovery (cdr) circuit in the event of loss of signal (los). design procedure clock mode selection the frequencies of the max3892 can be set up using clkset, rateset, and mode as shown in tables 2 and 3. layout techniques for best performance, use good high-frequency layout techniques. filter voltage supplies and keep ground connections short. use multiple vias where possible. also, use controlled-impedance transmission lines to interface with the max3892 clock and data inputs and outputs. exposed-pad package the ep 44-pin qfn incorporates features that provide a very low thermal-resistance path for heat removal from the ic to a pc board. the max3892? ep must be sol- dered directly to a ground plane with good thermal conductance. +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis 8 _______________________________________________________________________________________ slbpd slben slbo output v il x power-down slbo output v ih v il 622mhz/667mhz clock output v ih v ih 2.5gbps/2.7gbps system loop-back output table 1. loop-back operation mode clkset rateset rclk frequency (mhz) v cc 666 v cc gnd 622 v cc 166.5 open gnd 155.52 v cc 83.25 30k to gnd gnd 77.76 v cc 41.63 gnd gnd 38.88 table 2. setting the reference clock frequency mode rateset pclki frequency (mhz) sclko frequency (ghz) v cc 666hz 2.666 v cc gnd 622hz 2.488 v cc 666hz disabled open gnd 622hz disabled v cc 333hz disabled 30k to gnd gnd 311hz disabled v cc 333hz 2.666 gnd gnd 311hz 2.488 table 3. setting the clock mode
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis _______________________________________________________________________________________ 9 clkset reset mode fifoerror rateset sdo+ sdo- cml sclko+ sclko- cml slben slbo+ slbo- slbpd cml pclko+ pclko- lvds rclk+ rclk- lvpecl clk d 4-bit reg pclki+ pclki- lvds pdi[3..0]+ pdi[3..0]- lvds wr/rd 4 x 4 fifo 4:1 mux logic lol max3892 4 frequency generator figure 2. functional diagram 50 50 50 50 output circuit input circuit v cc v cc figure 3. current-mode logic
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis 10 ______________________________________________________________________________________ v od v os v oh v ol v od( p-p) |v od | +v od -v od 0 (diff) single-ended output (vpd+) - (vpd-) differential output figure 4. differential output levels gnd pdi0- pdi1- pdi1+ pdi2- pdi2+ pdi3- pdi3+ v cc gnd pdi0+ sclko- sclko+ vcco sdo- sdo+ vcco slbo- slbo+ vcco vcco gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 gnd v cc lol pclki+ gnd pclki- fifoerror reset slben slbpd v cc fil vccvco rateset clkset rclk- rclk+ v cc pclko- pclko+ gnd max3892 mode top view *the exposed paddle must be soldered to supply ground on the circuit board. *ep qfn/tqfn pin configuration chip information transistor count: 6210 package information (for the latest package outline information, go to www.maxim-ic.com/packages .) 21-0144 package type document no. 44 qfn 21-0092 44 tqfn
revision history rev 0; 11/01: original data sheet release. rev 1; 5/03: page 1: added package code; page 11: updated package drawing. rev 2; 3/06: page 1: updated typical application circuit; page 6: corrected pin numbers for v cc and vccvco; page 10: corrected pin names. rev 3; 6/06: page 4: updated ac table for jg conditions/typ, pj conditions, dj conditions, and added new note 7; page 5: added new toc5. rev 4; 12/06: page 1: removed future status from max3882 in typical application circuit; page 5: updated toc3. rev 5; 2/07: page 1: added lead-free package to ordering information table. rev 6; 10/07: page 1: clarified that the max3892eht+ is a tqfn package; page 10: added tqfn to the pin configuration; pages 11?2: removed package drawings and replaced with package type table. max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 11 2007 maxim integrated products is a registered trademark of maxim integrated products, inc.
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis english ? ???? ? ??? ? ??? ? ??????? login | register what's new products solutions design appnotes support sales about us my maxim maxim > products > optoelectronics > max3892 max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis overview technical documents ordering info related products user comments (0) all status active: in production. description data sheet the max3892 serializer is ideal for converting 4-bit-wide, 622mbps parallel data to 2.5gbps serial data in dwdm and sonet/sdh applications. a 4 x 4-bit fifo allows for any static delay between the parallel output clock and parallel input clock. delay variation up to a unit interval (ui) is allowed after reset. a fully integrated phase-locked loop (pll) synthesizes an internal 2.5ghz serial clock from a 622mhz, 155.5mhz, 77.8mhz, or 38.9mhz reference clock. a selectable dual vco allows excellent jitter performance at both sonet and forward-error correction (fec) data rates. operating from a single 3.3v supply, this device accepts low-voltage differential-signal (lvds) clock and data inputs for interfacing with high-speed digital circuitry, and delivers current-mode logic (cml) serial data and clock outputs. a loopback data output is provided to facilitate system diagnostic testing. the max3892 is available in the extended temperature range (-40c to +85c) in 44-pin qfn and tqfn packages. full data sheet download rev 6 (pdf, 188kb) e-mail an evaluation kit is available: max3892evkit key features applications/uses http://www.maxim-ic.com/datasheet/index.mvp/id/3215/t/al (1 of 5) [15-nov-2010 11:54:36 am]
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis l single +3.3v supply l 455mw power consumption l 1.4ps rms maximum jitter generation l 4 x 4-bit fifo input buffer l 622mbps/666mbps parallel to 2.5gbps/2.7gbps serial conversion l 622mhz/667mhz or 311mhz/333mhz clock input l on-chip clock synthesizer l multiple clock reference frequencies: m (622.08mhz, 155.52mhz, 77.76mhz, 38.88mhz) or (666.51mhz, 166.63mhz, 83.31mhz, 41.66mhz) l lvds parallel clock and data inputs l cml serial data and clock outputs l additional cml output for system loopback testing l add/drop multiplexers l backplane interconnect l dense digital cross-connects l sonet/sdh oc-48 transmission systems l wdm transponders key specifications: datacom serializers/deserializers part number functions target serial oper. range (gbps) v supply (v) i cc (ma) config. parallel i/f data rate (mbps) serial i/f data rate (mbps) parallel i/f logic lvls. serial i/f logic lvls. package/pins oper. temp. (c) price typ see notes max3892 datacom serializer 1 to 4.5 3.3 138 4-to-1 622/667 2488/2670 lvds cml qfn/44 tqfn/44 -40 to +85 $25.75 @1k see all datacom serializers/deserializers (10) pricing notes: this pricing is budgetary, for comparing similar parts. prices are in u.s. dollars and subject to change. quantity pricing may vary substantially and international prices may differ due to local duties, taxes, fees, and exchange rates. for volume-specific prices and delivery, please see the price and availability page or contact an authorized distributor. diagram http://www.maxim-ic.com/datasheet/index.mvp/id/3215/t/al (2 of 5) [15-nov-2010 11:54:36 am]
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis typical operating circuit application notes application note 462 hfan-04.0.2: converting between rms and peak-to-peak jitter at a specified ber application note 697 silicon germanium (sige) technology enhances radio front-end performance application note 995 max3892: 2.7gbps transponder applications using the max3892, max3882, and max3670 chipset application note 4613 a proposed framework for measuring, identifying, and eliminating clock and data jitter on high-speed serial communication links reliability reports reliability report: max3892.pdf show fit data for: software/models http://www.maxim-ic.com/datasheet/index.mvp/id/3215/t/al (3 of 5) [15-nov-2010 11:54:36 am]
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis max3892egh ibis model ordering information notes: 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales. 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt; -d = drypack; -u/+u on ds parts = cut tape. more: see full data sheet or maxim product naming conventions. 4. * some packages have variations, listed on the drawing. "pkgcode/variation" tells which variation the product uses. note that "+", "#", "-" in the part number suffix describes rohs status. package drawings may show a different suffix character. filters part number: package: temperature: tape and reel max3892 free sample buy status package: type pins footprint drawing code/var * temp rohs/lead-free? materials analysis max3892egh-td active qfn;44 pin;50.4 mm2 outline drawing:21-0092 (pdf) land pattern: 90-0223 (pdf) use pkgcode/variation: g4477-3* -40c to +85c rohs/lead-free: no materials analysis MAX3892EGH-D active qfn;44 pin;50.4 mm2 outline drawing:21-0092 (pdf) land pattern: 90-0223 (pdf) use pkgcode/variation: g4477-3* -40c to +85c rohs/lead-free: no materials analysis max3892eth+t active tqfn;44 pin;50.4 mm2 outline drawing:21-0144 (pdf) land pattern: 90-0127 (pdf) use pkgcode/variation: t4477+2* -40c to +85c rohs/lead-free: lead free materials analysis max3892eth+ active tqfn;44 pin;50.4 mm2 outline drawing:21-0144 (pdf) land pattern: 90-0127 (pdf) use pkgcode/variation: t4477+2* -40c to +85c rohs/lead-free: lead free materials analysis similar products by function http://www.maxim-ic.com/datasheet/index.mvp/id/3215/t/al (4 of 5) [15-nov-2010 11:54:36 am]
max3892 +3.3v, 2.5gbps/2.7gbps, sdh/sonet 4:1 serializer with clock synthesis see all datacom serializers/deserializers (11 products) similar products by application passive optical network (pon) > ont serializer evaluation kits max3892evkit evaluation kit for the max3892 products with similar part numbers max3892evkit evaluation kit for the max3892 more information new product press release [ 2001-12-05 ] didn't find what you need? l next day product selection assistance from applications engineers l parametric search l applications help document ref.: 19-2215 rev 6; 2007-10-26 this page last modified: 2007-10-26 ? ? ? privacy policy ? legal notices copyright ? 2010 by maxim integrated products http://www.maxim-ic.com/datasheet/index.mvp/id/3215/t/al (5 of 5) [15-nov-2010 11:54:36 am]

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